This invention relates to designing integrated circuit (IC) chips, and particularly to changing clock delays within a clock net of a complex application specific integrated circuit (ASIC). Most particularly, the invention is directed to changing the clock delay within a clock net for skew optimization, and to changing and budgeting clock delays between several clock nets of an ASIC to achieve optimal global clock delay and skew.
Problems associated with timing closure of clock nets in ASICs increase with the complexity of ASIC designs and the need for higher operating frequencies of ASIC chips. Presently, timing closure is resolved using clock optimization techniques that address the clock logics separately from the data logics. While the clock optimization problem might be simplified by separating clock logics and data logics in synthesis, this technique also reduces the optimization potential by dividing a single two-dimensional optimization problem into two one-dimensional problems.
The data logics affect timing closure in clock logics. Consequently, the one-dimensional problem solution addressing only the clock logics did not always lead to optimal clock balance between different clock nets. As a result, new optimization techniques are needed to implement the designs more efficiently.
To achieve better timing results, the present invention provides an integrated approach whereby the clock logics are synthesized and optimized simultaneously with the data logics. The clock logics are restructured based on the timing information of the data logics so that the clock delays (or useful skews) can be used to fix timing violations.
In one embodiment, clock delays are balanced for optimization of clock skew in a clock net of an ASIC by restructuring part of the net. The clock net has at least one clock source. Clock cells to be balanced are selected and a slack is calculated for each selected clock cell based on an insertion delay associated with the clock source and the clock arrival and transition times required by the selected clock cell. The cell delay is adjusted based on the calculated slack.
In other embodiments, groups of clock domains having timing paths between them are identified. Clock insertion delays are equalized for all clock domains of the group. Preferably, clock insertion delay equalization is performed using buffers and an additional delay coefficient. The clock insertion delays are changed by restructuring the buffers to optimize paths between different clock domains.
In other embodiments, clock pins having timing violations are identified based on both clock delay and data delay. The clock net is restructured to optimize timing in the domain.
In one embodiment, the invention is manifest as a computer readable program containing code that, when executed by a processor, causes the processor to balance clock delays to optimize skew in the clock network of an ASIC. More particularly, a storage medium contains processor executable instructions that enable the processor to perform the processes of the invention and alter the clock network to adjusting the cell delay.